1. Field of the Invention
Embodiments if the invention relate to nonvolatile semiconductor memory devices and related programming methods. More particularly, embodiments of the invention relate to a nonvolatile semiconductor memory device having a wired-OR page buffer and a related method of programming.
This application claims priority to Korean Patent Application No. 2005-02191 filed on Jan. 10, 2005, the subject matter of which is hereby incorporated by reference.
2. Discussion of Related Art
Generally, read and programming operations for memory cells in a nonvolatile semiconductor memory device are carried out by controlling bit line voltages corresponding to selected memory cells. In order to properly drive bit lines voltages during a read or programming operation, contemporary nonvolatile semiconductor memory device provide one or more page buffers to temporarily store the data to be programmed into or read from the memory cells.
Figure (FIG.) 1 is a diagram illustrating a conventional nonvolatile semiconductor memory device, and FIG. 2 is a diagram illustrating a typical column gate (YG) corresponding to one page buffer (PBP) shown in FIG. 1. The conventional semiconductor memory device nominally comprises a memory cell array 10 comprising a plurality of memory cells, connected to a plurality of “n” page buffers (PBP). Each page buffer (PBP) is connected to a global data line (GDL) through a column gate (YG).
Each page buffer (PBP) comprises a sense latch 150, precharge circuit 140, a bit line (BL) shielding block 120 and a BL bias circuit 110. In the conventional page buffer (PBP), data to be written to a selected memory cell is loaded and latched in sense latch 150. Data stored in sense latch 150 is thus provided to bit line BLe or BLo through BL shielding block 120 and BL bias circuit 110. Thereafter, a programming operation is performed relative to the selected memory cell. In similar fashion, data to be read from a selected memory cell is temporarily stored in sense latch 150. Data thus stored in sense latch 150 may be transferred to the global data line (GDL) in response to a column gate signal (not shown).
However, in the conventional nonvolatile semiconductor memory device, as illustrated in FIGS. 1 and 2, internal data lines (IDL) connect each page buffer (PBP) to the global data line (GDL) through a corresponding the column gate (YG). This data transmission path includes a sense latch node (NLATP) which is commonly used in read and programming operations for the memory device. In the illustrated example of a conventional nonvolatile semiconductor memory device, data stored at the sense latch node (NLATP) of the page buffer (PBP) may be “flipped” (i.e., logically inverted) by a charge sharing effect between the global data line (GDL) and the internal data lines (IDL).
This possibility requires that the conventional nonvolatile semiconductor memory device perform a program-verifying operation. This is typically accomplished using a Y-scanning scheme that confirms data for each memory cell on a memory cell by memory cell basis. As a result, the conventional nonvolatile semiconductor memory device suffers from temporally extended operation cycles as necessitated by the program-verifying operation.
In a separate vein, conventional nonvolatile semiconductor memory devices typically require a cache function whereby a next page of data to be programmed is loaded into a cache latch associated with each page buffer. This cache function is usually performed during a programming operation associated with a page of data that has previously been loaded. This cache function allows the programming speed for the memory device to be enhanced where sequential pluralities of data are programmed into a memory page.